Refresh control circuit for ICs with a memory array

ABSTRACT

An IC having an array of memory cells that can be accessed through two different ports is described. Read/write operation is performed through one of the ports. The refresh of the memory cell is performed through the other port. In one embodiment, the other port is only used internally to the memory array.

BACKGROUND OF INVENTION

[0001] Integrated circuits can include an array of dynamic random accessmemory cells (DRAM). A DRAM cell includes a storage capacitor forstoring a charge that represents, for example a logic “0” or “1”. Sincethe charge stored within the cell capacitor leaks due to parasiticcurrent paths, the charge has to be refreshed periodically. The timebetween two refresh events of the same memory cell is called retentiontime. The retention time is set such that the storage capacitor hasalways enough charge so that it can be detected by a sense amplifier. Arefresh operation is usually performed for a complete row of memorycells within the memory cell array. During a refresh cycle, theinformation stored in the memory cells of a row is read out, amplified,and written back into the memory cells. The size of a memory cell of aDRAM is small so that dynamic memories provide for a high cell count ona single chip. A refresh operation, however, is time-consuming and slowsdown the operation of a DRAM.

[0002] From the foregoing discussion, it is desirable to provide arefresh scheme which reduces the adverse impact to performance.

SUMMARY OF INVENTION

[0003] The invention relates generally to ICs with a memory array ofmulti-port memory cells. More particularly, the invention relates torefreshing of multi-port memory cells. In one embodiment, the memoryarray comprises dual port memory cells. An external access to aparticular memory cell is performed through one of the access ports. Theother access port is not accessible by external signals and is hiddenfrom the outside. The other port performs the refresh of the memory cellarray. A particular memory cell is coupled to the first access port inorder to read or write data signals. The memory cell is also coupled tothe second port in order to be refreshed.

[0004] In one embodiment, the external interface of the memory device iscomparable to a SRAM device. The interface of the memory device of theinvention does not need a refresh that is initiated from memory externaldevices. However, since dynamic memory cells are used, a refreshoperation is performed internally and is transparent to the environmentof the system.

[0005] As an advantage of the invention, an SRAM functionality isachieved, although the internal structure of the memory device usesdynamic memory cells. The memory cells have two selection transistorswhich connect the storage node of the cell to the first and secondports. The read and write operations from the exterior are performedthrough one of the ports. A refreshing is performed through the otherport of the memory cell.

[0006] Special arrangements are provided to hide the internal refreshoperation from the outside environment. In particular, a contentiondetection monitors if a read/write access and a refresh operation aresubject to a particular row of memory cells. If the row address of aread/write access and the row address of a refresh operation are thesame, the refresh operation is suppressed for this particular row andthe read/write access is preferred over the refresh operation. Duringthe read/write access to a memory cell, the row within which the memorycell is located is inherently refreshed. In case of a contention, it ispossible to keep the refresh operation idle or, alternatively, to simplyskip the refresh for the row of the read/write access and perform therefresh operation for the next row within the same cycle.

[0007] Another aspect of the invention is the generation of the refreshaddress clock signal which operates the refresh address counter. In thenormal operation mode of the memory device, a clock signal is providedto one of the input terminals of the memory device. Usually, datasignals are provided in synchronism with the system clock signal. Duringpower-down mode, the clock signal may be absent in order to save power.The refresh operation during the power-down mode is switched to areference clock signal which is usually also provided to the memorydevice. The reference clock may be generated by a quartz oscillator. Thequartz oscillator frequency can be considerably lower than the frequencyof the system clock. The refresh control circuit has suitable devices tosynchronize the refresh operation with the system clock or with thereference clock depending on whether the normal operation mode or thepower-down mode is operative.

[0008] The memory device may have separate sense amplifiers for the dataread/write operations and the refresh operations. The sense amplifiersfor read/write operations are connected to the first port of a memorycell and are connected to the peripheral data input/output circuits. Theread/write sense amplifiers are connected to a column decoder that isable to select at least one of the sense amplifiers in response to acolumn address signal so that a data path is established to theperipheral input/output circuitry. The refresh sense amplifiers areactivated altogether so that a row of memory cells can be refreshed at atime.

[0009] The particular timing of a number of signals that control thesequence of a refresh operation is generated by a finite state machineand is distributed to the memory cell array and to the refresh rowdecoder.

[0010] The refresh addresses generated by the refresh control circuitmay be provided to different memory blocks in parallel. A selectionbetween the different blocks is made through a particular bit of arefresh enable signal that enables the refresh within one of the blocksat a time. Preferably, the blocks are activated for a refresh, one afterthe other so that a continuous address space of row addresses to berefreshed is achieved.

BRIEF DESCRIPTION OF DRAWINGS

[0011]FIG. 1 shows a block diagram of a memory array in accordance withone embodiment of the invention;

[0012]FIG. 2 shows a functional block diagram of a refresh controlcircuit in accordance with one embodiment of the invention;

[0013]FIG. 3 shows the timing of clock signals and the refresh enablesignal which control a refresh operation in accordance with oneembodiment of the invention;

[0014]FIG. 4 shows a memory array in accordance with an alternativeembodiment of the invention; and

[0015]FIG. 5 shows a memory cell in accordance with one embodiment ofthe invention.

DETAILED DESCRIPTION

[0016]FIG. 1 shows a block diagram of an array 100 of memory cells 13 inaccordance with one embodiment of the invention. The array can be partof an IC, such as a system-on-chip (SOC). Other types of ICs, such asmemory ICs, are also useful. The array includes a bank of memory cells.The memory cells are interconnected by bitlines 83 in the columndirection 15 and wordlines 14 in the row direction 16. The bitlines arecoupled to sense amplifiers 85 to facilitate memory accesses. First andsecond bitlines are coupled to a sense amplifier to form a bitline pair.The memory array can be provided with more than one bank. Preferably,for multiple bank arrays, the number of banks is equal to 2^(n), where nis a whole number. Other number of banks is also useful.

[0017] In one embodiment, the bank is separated into first and secondblocks 1 and 2, each with a plurality of memory cells interconnected bybitlines 83 in the column direction and wordlines 14 in the rowdirection. The memory cells are arranged in an open bitlinearchitecture. In an open bitline architecture, one bitline from eachblock is coupled to the same sense amplifier. Other memoryarchitectures, such as folded bitline, are also useful. For example, thebitlines of a bitline pair are adjacent to each other in a foldedbitline architecture. In one embodiment, the memory array comprises dualport memory cells. A memory cell is coupled to first and second bitlinesand first and second wordlines. As such a row of memory cells arecoupled to first and second wordlines 14 a-b and a column of memorycells is coupled to first and second bitlines 83 a-b. Alternatively, thememory array comprises memory cells with more than two ports.

[0018] The first and second wordlines are coupled to first and secondrow decoders 11 a-b. In one embodiment, the wordlines of the first blockare coupled to first and second row decoders 11 a ₁ and 11 b ₁ and thewordlines of the second block are coupled to first and second rowdecoders 11 a ₂ and 11 b ₂. Although the first and second wordlinedecoders are depicted as separate adjacent decoders, it is understoodthat decoders can be a plurality of segments in which alternatingsegments are from respective first and second decoders. Thisconfiguration advantageously allows the decoder segments to be alignedto respective wordlines. A first wordline is activated through the firstrow decoder and a second wordline is activated through the row decoder.

[0019] First and second sense amplifier banks 85 a-b having a pluralityof sense amplifiers are coupled to first and second bitlines tofacilitate memory accesses. The first bitlines of the memory cells arecoupled to first sense amplifier bank while the second bitlines of thememory cells are coupled to the second sense amplifier bank.

[0020] A sense amplifier is coupled to two first or two second bitlinesof the memory cells to form a bitline pair. A memory cell is selectedfrom one of the bitline pair (selected bitline) while the other bitlineserves as a reference bitline. In one embodiment, the memory array isarranged in an open bitline architecture. In an open bitlinearchitecture, the bitlines of a bitline pairs are in different memoryblocks. For example, a sense amplifier is coupled to a first bitlinefrom the first block and a first bitline from the second block.Providing a memory array arranged in other types of bitlinearchitectures, such as open or open-folded, is also useful.

[0021] In one embodiment, the first port of the memory cells serves asaccess port and the second port serves as refresh port. The refreshoperations are completely internal to the memory array. By providing adedicated refresh port, the memory array can achieve SRAM functionalityon the system level while using dynamic memory cells for informationstorage. Since multi-port DRAM cells are smaller in size than SRAMcells, their use advantageously results in reduced chip size.

[0022] To perform a memory access, such as a read/write access,appropriate external signals are provided through respective controlinput terminals 7. For example, the first row decoder is operated inresponse to an address signal ADR on signal line 71, a read/write signalR/W on signal line 72, and a chip select signal CS on signal line 74.For a synchronous memory system, a system clock signal CLK can beprovided on signal line 73. Alternatively, no CLK signal is needed forasynchronous systems. The memory cell corresponding to the ADR isaccessed. In one embodiment, an alternative OSC clock signal forexample, from an oscillator, can be provided on signal line 75.

[0023] For a read access, the information stored in the accessed memorycell is made available on the first bitline and is sensed in senseamplifier of the first sense amplifier bank. An output of the senseamplifier is selected through a column decoder so that the output signalof the sense amplifier is forwarded to peripheral circuitry 3 whichdrives the data onto output signal terminal 31. For a write operation, adata-in signal is applied to input terminal 32 and is distributedthrough the data path back to the selected memory cell. The senseamplifier is also connected to first bitline in second memory cellblock, which functions as a reference bitline. Although the input andoutput terminals are depicted as separate terminals, it is understoodthat a single bi-directional terminal can be provided instead.

[0024] The charge stored in the memory cells of the array dissipatesover time and needs to be refreshed in order to maintain the datastored. In one embodiment, a refresh operation refreshes a row of memorycells simultaneously. To perform a refresh to a row, the second orrefresh row decoder activates the refresh wordline of the row to berefreshed. For example, a row in the first block is refreshed. Theinformation stored in memory cells of the row are read, sensed by thesecond or refresh amplifier banks, and written back into the memorycells of the refreshed row. The second bitlines of the second blockserves as reference refresh bitlines for the sense amplifier bank.

[0025] The control signals for performing a refresh operation isgenerated by a refresh control circuit 6. The refresh operation inaccordance with one embodiment of the invention is described inconjunction with FIGS. 2-3. A refresh enable signal RE indicates theactivation of a refresh operation. The time between two successiverefresh cycles is referred to as the retention time R. The retentiontime R may be In this case, the retention time can be set after theproduction of the memory chip during test measurements which determinethe amount of leakage in order to fine-tune the setting of the retentiontime. The set values for the retention time can be permanentlyprogrammed by, for example, fuses 63. Also the control of the retentiontime can be designed to be dynamic through a reference discharge pathin, for example, the array. When the charge that passes through thedischarge path exceeds a threshold value, a refresh enable pulse RE isactivated. In one embodiment, the discharge path comprises a referencememory cell having a similar design as the memory cells of the array.Other techniques for determining the retention time are also useful.

[0026] The addresses RADR of the rows of the memory cells to berefreshed are generated by refresh address counter 64. The clock signalCLK′ provides the counting pulse for refresh address counter 64. Therefresh address counter 64 is enabled by the refresh enable signal RE.In one embodiment, the refresh counter counts the cycles based on thesystem clock CLK (e.g., refresh controlled by CLK signal). In analternative embodiment when the system clock is disabled duringpower-down mode (e.g., power-down signal PD=1), an oscillator clock OSCis provided by a reference oscillator, preferably a quartz oscillator62, controls the refresh address counter 64.

[0027] The quartz oscillator clock OSC, in one embodiment, has a muchlower frequency than the system clock CLK and may include a phase shiftcompared to the system clock CLK. The switching from normal operation topower down mode (PD=1) or vice-from power down mode to normal operation(PD=0) can occur during a refresh period (RE=1). In this case, therefresh clock CLK′ should be synchronized either to the system clock CLKor to the quartz oscillator clock OSC in order to ensure that therefresh operation is completed without error. If synchronization of therefresh address counter clock CLK′ to the clock sources CLK or OSC couldnot be achieved,,a particular row of memory cells would be skippedduring refresh and the stored information may be destroyed.

[0028] During a standby mode (STBY=1), the IC is fully shut down, and itis not desired to maintain the storage of information. During standby ofthe IC, the refresh signal generation is stopped.

[0029] In one embodiment, all the above functionality, including refreshsignal generation, clock synchronization, and refresh enabling, isprovided by the refresh control circuit 6, in particular in portion 61of the refresh control circuit 6.

[0030] The refresh enable signal can be provided as one continuousactive impulse and an idle portion as shown in FIG. 3, alternatively,the active pulses of the refresh enable signal are shorter and aredistributed preferably equally over the retention time interval. Theperiodicy of the active pulses equals the retention time. During theretention time interval R all the memory cells need to be refreshed. Forexample, when N rows of the memory device are to be refreshed, there areN active pulses of the refresh enable signal, preferably at equidistanttime instances distributed over the retention time period R.

[0031] The refresh address RADR indicates the row of memory cells onwhich the refresh operation is currently performed. For example, therefresh address row decoder 12 activates wordline 14 b of row 16 so thatthe charge stored in the memory cells of row 16 are output in parallelto the refresh amplifiers in amplifier bank 86. The amplifiers in bank86 amplify the small signals received from row 16. After sufficientamplification, the amplified signals are written back into the memorycells of row 16 and the wordline 14 b is disabled. When at the same timeor within the same clock cycle a read/write access is requested throughan address ADR supplied to the external address lines 71, a contentiondetection and handling takes place in function block 65 of refreshcontrol circuit 6. In this case when the row portion of the externaladdress ADR and the refresh address RADR are the same, the refresh forthe particular row of memory cells, (e.g., row 16) is suppressed and adata read or a data write depending on the state of the read/writesignal R/W is performed. The refresh operation can be idle or therefresh can be performed on a different row, preferably the next rowhaving an address which is incremented by one. It is also possible torefresh another row of memory cells, alternatively. This scheme ofcontention detection is possible due to the fact that when a piece ofinformation is read out or written into one of the memory cells of arow, (e.g., memory cell 13 of row 16), the contents of all memory cellsof the particular row are output onto the bitlines that are connected tothe sense amplifiers of amplifier bank 85. Comparable to a refreshoperation, the signals are amplified by the amplifiers of bank 85 and,even during a read cycle, are written back into the respective memorycells.

[0032] In one embodiment, the particular sequencing of signalsperforming a refresh operation on a particular row is performed by afinite state machine 66. The refresh control signals on signal linesinclude, for example, precharge control, decoder select, selection ofn-channel-transistor sense amplifier portion, and p-channel-transistorsense amplifier portion. Another sequencing of control signals is alsouseful. The sequencing of the control signals can be in-phase to theclock signal or out-of-phase to the clock signal. The contentiondetection has to be adopted correspondingly. The respective refreshcontrol signals present on signal lines are propagated over suitablesignal paths to the appropriate circuit elements in the memory device ofFIG. I in order to perform the refresh operation as explained above.

[0033] As shown in FIG. 1, the memory cell array comprises a bank whichis divided into two different blocks. The first and second blocks arearranged in an open bitline architecture. Arranging the bank with othertypes of bitline architectures, such as folded, is also useful.Providing an array with multiple banks is also useful.

[0034] Illustratively, as shown in FIG. 4, the array can be organizedinto four banks 111, 112, 113, 114 of memory cells, each bank having nrows of memory cells. For example, n is equal to 256. Providing n equalto other values can also be useful. Preferably, n is equal to 2^(x),where x is a whole number. The memory cells of a bank can be arranged inan open-bitline architecture. Other types of architectures, such asfolded, are also useful.

[0035] The refresh addresses RADR generated in refresh control block 67are provided to all banks 111-114 in parallel. The refresh operationwithin one of the banks, in one embodiment, is enabled by a differentrefresh enable signal RE0, RE1, RE2, and RE3, respectively. In oneembodiment, only one of the refresh enable signal is activated at atime. Alternatively, all or some of the refresh enable signals areactivated at the same time. This can be facilitated by, for example,providing all or some common refresh enable signals. Refreshing morethan one bank at a time increases refresh performance. The increase inperformance, however, requires more peak power. The refresh, in oneembodiment, is selected to optimize performance and power requirements.

[0036]FIG. 5 shows a dual port memory cell in accordance with oneembodiment of the invention. The memory cell comprises a storagetransistor 115. The gate electrode of the storage transistor 115 isconnected to a reference potential, e.g., the positive power supplyV_(DD). One end of the drain source path of storage transistor 15 isconnected to a selection transistor 116, the gate of which beingconnected to 40 and another end of its drain source path being connectedto bitline 83. The other end of the drain source path of storagetransistor 115 is connected to a second selection transistor 117, thegate of which being connected to wordline 42 and another end of itsdrain source path being connected to bitline 84. In one embodiment, alltransistors of the memory cell are n-FETs. Providing p-FETS or acombination of n-type and p-type FETs is also useful. Alternatively, thestorage transistor 115 can be replaced by a storage capacitor. Othertypes of multi-port memory cells are also useful.

[0037] The invention has been particularly shown and explained inconjunction with various useful or alternative embodiments. It will berecognized by those skilled in the art that modifications and changesmay be made to the present invention without departing from the spiritand the scope thereof. The scope of the invention should therefore bedetermined not with reference of the above description of theembodiment, but with reference to the appended claims along with theirfull scope, including any equivalents.

1. A memory device, comprising: a memory cell array having a multitudeof memory cells, first and second bitlines, and first and secondwordlines, each of said memory cells being coupled to one of said firstbitlines, one of said second bitlines, one of said first wordlines, andone of said second wordlines; each of said memory cells being accessiblethrough one of said first wordlines and one of said first bitlines by anexternal port and being accessible through one of said second wordlinesand one of said second bitlines by an internal port; said external portbeing connected to input terminals to receive input signals in order toselect one of said memory cells for an external data access; and arefresh control unit generating refresh control signals to access one ofsaid memory cells to perform a refresh of the respective one of saidmemory cells through said internal port.
 2. The memory device accordingto claim 1, wherein each one of said memory comprises: a first selectiontransistor coupled to one of said first wordlines and one of said firstbitlines; a second selection transistor coupled to one said secondwordlines and one of said second bitlines; and a storage node connectedto said first selection transistor and said second selection transistor.3. The memory device according to claim 2, wherein each one of saidmemory comprises: a storage transistor having a drain/source path and agate terminal, said drain/source path being connected to said first andsaid second selection transistors; and said gate terminal beingconnected to a reference potential.
 4. The memory device according toclaim 1, wherein said external port is connected to input terminalsdesigned to receive one of an address signal, a signal determining aread or a write operation, a data clock signal, and a device selectsignal.
 5. The memory device according to claim 4, wherein said internalport is hidden from said address signal, said signal determining a reador a write operation, and said device select signal.
 6. The memorydevice according to claim 1, comprising: a first bank of senseamplifiers, wherein each one of said first bitlines is connected to oneof said sense amplifiers of said first bank; a column decoder, whereinan individual one of said sense amplifiers of said first bank can beselected to perform one of data read to an external terminal; and datawrite from an external terminal.
 7. The memory device according to claim6, comprising: a second bank of sense amplifiers, wherein each one ofsaid second bitlines is connected to one of said sense amplifiers ofsaid second bank, and wherein multiple of said amplifiers are selectedto perform a refresh of a row of memory cells.
 8. The memory deviceaccording to claim 1, comprising: a first clock terminal to receive asystem clock signal to synchronize external data input and output; asecond clock terminal to receive a reference clock signal; and asynchronization circuit to output a refresh clock signal which issynchronized to one of said system clock or said reference clocksignals.
 9. The memory device according to claim 8, comprising: arefresh address counter to generate row addresses of rows of memorycells to be refreshed, said address counter being controlled by saidrefresh clock.
 10. The memory device according to claim 1, comprising: acontention detection circuit, said contention detection circuitreceiving a row address in response to an external read or write accessthrough said external port and receiving a refresh address for a row ofmemory cells to be refreshed, said contention detection circuitsuppressing a refresh, if said refresh address equals said row address.11. The memory device according to claim 1, wherein said memory cellarray comprises at least two blocks of memory cells, said blocks beingprovided with a refresh row address in parallel, said refresh controlcircuit generating a separate refresh enable signal for each of saidblocks to perform a refresh operation for one of said blocks subsequentto a refresh operation for another one of said blocks.
 12. A memorydevice, comprising: a memory cell array having memory cells, each ofsaid memory cells being accessible through a first port and through asecond port, only said first port of said first and second ports beingaccessible by an external address signal to select one of said memorycells; and a refresh control circuit designed to generate refreshcontrol signals to refresh said memory cells through said second port.13. The memory device according to claim 12, comprising: a contentiondetection circuit receiving a refresh address to access a subset of saidmemory cells and an address to access at least of one said memory cellsof said subset of memory cells for an external read or write operation,said contention detection circuit suppressing a refresh operation forsaid subset of said memory cells.
 14. The memory device according toclaim 13, wherein a refresh operation is performed for another subset ofmemory cells.
 15. The memory device according to claim 13, wherein saidsubset of memory cells is a row of memory cells.
 16. The memory deviceaccording to claim 12, wherein said refresh control circuit receives asystem clock signal and a reference clock signal, said refresh controlcircuit has a refresh address counter to provide a sequence of addressesfor subsets of memory cells to be refreshed, said memory device having anormal mode and a power-down mode, wherein said refresh address counteris controlled by said system clock signal during the normal mode and iscontrolled by said reference clock signal during the power-down mode.17. The memory device according to claim 16, wherein said refreshcontrol circuit comprises a synchronization circuit that synchronizes aclock signal to one of said system clock or reference clock signals inresponse to one of said normal or power-down modes, wherein said clocksignal controls said refresh address counter.
 18. The memory deviceaccording to claim 16, wherein said reference clock signal has a lowerfrequency than said system clock signal.
 19. The memory device accordingto claim 12, wherein each one of said memory cells comprises: a firstselection transistor coupled to one of said first wordlines and one ofsaid first bitlines and a second selection transistor coupled to onesaid second wordlines and one of said second bitlines; and a storagenode connected to said first selection transistor and said secondselection transistor.
 20. A memory device, comprising: a memory cellarray having a multitude of memory cells arranged in rows; a first rowdecoder to activate one of said rows in response to an external address;a second row decoder to activate one of said rows in response to aninternal address; and a refresh control circuit to refresh the memorycells of a row which is activated by said second row decoder.
 21. Thememory device according to claim 20, wherein said refresh controlcircuit comprises a contention detection circuit suppressing the refreshoperation when the row to be activated by said first row decoder and therow to be activated by said second row decoder are the same row.
 22. Thememory device according to claim 20, wherein each one of said memorycells comprises a first selection transistor connected to the first rowdecoder through a first wordline and a second selection transistorconnected to the second row decoder through another wordline and astorage node coupled to the first and the second selection transistors.